Semiconductor device manufacturers are constantly improving device performance while lowering their cost of manufacture. One way manufacturers have reduced costs has been to shrink the sizes of the devices so that more devices can be made from a single semiconductor wafer. However, in reducing the device sizes other factors arise that limit their performance. For example, as the semiconductor devices are made smaller or shrunk, the source-drain breakdown voltage decreases, junction capacitance increases, and the threshold voltage becomes unstable. Collectively, these adverse performance effects are referred to as short channel effects. Typical techniques for mitigating short channel effects rely on adjusting the electric field in the channel region to minimize the peak lateral electric field of the drain depletion region.
In addition to increasing device density, shrinking semiconductor device sizes decreases their gate width, which in turn reduces their channel lengths and improves transistor performance. However, as the gate width is decreased, it becomes increasingly difficult to form silicide on the gate structures. The inadequate formation of silicide results in an increase in the gate resistance. Because silicide lowers gate resistance and improves transistor performance, it is desirable to efficiently and reliably form silicide on the gate structures. FIG. 1 is a cross-sectional side view of a portion of a prior art semiconductor component 10 during an intermediate stage of manufacture. What is shown in FIG. 1 is a semiconductor substrate 12 having a major surface 14. A gate structure 16 comprising a gate oxide 18 and a gate 20 having sidewalls 22 is disposed on major surface 14. Semiconductor component 10 includes a source extension region 24, a drain extension region 26, a source region 28, and a drain region 30. Oxide spacers 32 are formed adjacent sidewalls 22 and nitride spacers 34 are formed adjacent oxide spacers 32. Oxide spacers 32 offset the extension implants that form source and drain extension regions 24 and 26, respectively, from gate sidewalls 22. Nitride spacers 34 offset the deep source and drain regions 28 and 30, respectively, from the respective source and drain extension regions 24 and 26. A layer of refractory metal 36 is formed on gate 20, source region 28, and drain region 30. As those skilled in the art are aware, silicide is formed from the portions of the source and drain regions 28 and 30, respectively, and the portion of gate 20 that are in contact with refractory metal layer 36. With respect to gate 20, spacers 32 and 34 limit formation of silicide to its top surface. Because gate resistance is dependent upon the amount of gate surface area available for silicide formation, limiting the amount of available gate surface area for silicide formation limits the ability to lower the gate resistance.
Accordingly, what is needed is a semiconductor component having narrow gate widths and a method for manufacturing these semiconductor components which allows sufficient silicide formation so that the gate resistance remains low.